Timing
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
IEEE Transactions on Circuits and Systems II: Express Briefs
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Wire synthesizable global routing for timing closure
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
Optimization of the maximum delay of global interconnects during layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate estimation of global buffer delay within a floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MaizeRouter: Engineering an Effective Global Router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RICE: rapid interconnect circuit evaluation using AWE
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing congestion estimation with real design constraints
Proceedings of the 50th Annual Design Automation Conference
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For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion- and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm.