Approximation schemes for the restricted shortest path problem
Mathematics of Operations Research
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
Polynomial time approximation algorithms for multi-constrained QoS routing
IEEE/ACM Transactions on Networking (TON)
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect synthesis without wire tapering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An O(bn2) time algorithm for optimal buffer insertion with b buffer types
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A faster approximation scheme for timing driven minimum cost layer assignment
Proceedings of the 2009 international symposium on Physical design
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
Proceedings of the 46th Annual Design Automation Conference
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Delay-driven layer assignment in global routing under multi-tier interconnect structure
Proceedings of the 2013 ACM international symposium on International symposium on physical design
CATALYST: planning layer directives for effective design closure
Proceedings of the Conference on Design, Automation and Test in Europe
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As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasingly resistive which makes it more difficult to propagate signals across the chip. However, more advanced technologies (65nm and 45nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing, however, routability of the design may be hurt. The challenge is to assign minimal amount of wires to thick metals to meet timing constraints. In this paper, the minimum cost layer assignment problem is proven to be NP-Complete. As a theoretical solution for NP-complete problems, a polynomial time approximation scheme is proposed. The new algorithm can approximate the optimal layer assignment solution by a factor of 1 + ε in O(m log log m · n3/ε2) time for 0 n is the number of nodes in the tree and m is the number of routing layers. This work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem. In addition to its theoretical guarantee, the new algorithm is highly practical. Our experiments on 500 testcases demonstrate that the new algorithm can run 2x faster than the optimal dynamic programming algorithm with only 2% additional wire.