Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat
Proceedings of the 2004 international symposium on Physical design
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Flexible Data Structure for Efficient Buffer Insertion
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Fast algorithms for slew constrained minimum cost buffering
Proceedings of the 43rd annual Design Automation Conference
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A faster approximation scheme for timing driven minimum cost layer assignment
Proceedings of the 2009 international symposium on Physical design
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Proceedings of the 49th Annual Design Automation Conference
Depth controlled symmetric function fanin tree restructure
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimization, buffer insertion is indispensable in the physical synthesis flow. Buffering is known to be NP-complete and existing works either explore dynamic programming to compute optimal solution in the worst-case exponential time or design efficient heuristics without performance guarantee. Even if buffer insertion is one of the most studied problems in physical design, whether there is an efficient algorithm with provably good performance still remains unknown. This work settles this open problem. In the paper, the first fully polynomial time approximation scheme for the timing driven minimum cost buffer insertion problem is designed. The new algorithm can approximate the optimal buffering solution within a factor of 1 + ε running in O(m2n2b/ε3 + n3b2/ε) time for any 0 n is the number of candidate buffer locations, m is the number of sinks in the tree, and b is the number of buffers in the buffer library. In addition to its theoretical guarantee, our experiments on 1000 industrial nets demonstrate that compared to the commonly-used dynamic programming algorithm, the new algorithm well approximates the optimal solution, with only 0.57% additional buffers and 4.6x speedup. This clearly demonstrates the practical value of the new algorithm.