Approximation schemes for the restricted shortest path problem
Mathematics of Operations Research
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
An improved FPTAS for restricted shortest path
Information Processing Letters
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect synthesis without wire tapering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An O(bn2) time algorithm for optimal buffer insertion with b buffer types
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
Proceedings of the 46th Annual Design Automation Conference
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Proceedings of the 49th Annual Design Automation Conference
| Hi-index | 0.00 |
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignment manifests enormous potential in drastically reducing wire delay. This is due the fact that wires on thick metals are much less resistive than those on thin metals. Nevertheless, it is not desired to assign all wires to thick metals and the right strategy is to only use minimal thick-metal routing resources for meeting the timing constraints. This timing driven minimum cost layer assignment problem is NP-Complete, and a fast algorithm with provable approximation bound is highly desired. In this paper, a new fully polynomial time approximation scheme is proposed. It is based on a linear-time dynamic programming algorithm for bounded-cost layer assignment and efficient oracle queries. The proposed algorithm can approximate the optimal layer assignment solution in O(mn2/ε) time within a factor of 1+ε for any ε0, where n is the tree size and m is the number of routing layers. This significantly improves the previous work. The new algorithm is also highly practical. Our experiments on industrial netlists demonstrate that the new algorithm runs up to 6.5times faster than the optimal dynamic programming with few percent additional wire as guaranteed theoretically. This gives another 2x speedup over the previous work.