Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal non-uniform wire-sizing under the Elmore delay model
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Timing optimization for multi-source nets: characterization and optimal repeater insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global interconnect sizing and spacing with consideration of coupling capacitance
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
EWA: exact wiring-sizing algorithm
Proceedings of the 1997 international symposium on Physical design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
A performance-driven layer assignment algorithm for multiple interconnect trees
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An efficient hierarchical timing-driven Steiner tree algorithm for global routing
Integration, the VLSI Journal
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
Wire sizing with scattering effect for nanoscale interconnection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Wire shaping of RLC interconnects
Integration, the VLSI Journal
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
Wire sizing and spacing for lithographic printability and timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire sizing alternative: an uniform dual-rail routing architecture
Proceedings of the conference on Design, automation and test in Europe
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A faster approximation scheme for timing driven minimum cost layer assignment
Proceedings of the 2009 international symposium on Physical design
Elmor model-based algorithm to select optimal connections on the clock tree
Automation and Remote Control
A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
IEEE Transactions on Circuits and Systems II: Express Briefs
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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In this paper, we study the optimal wiresizing problem under the Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we have developed a polynomial-time optimal wiresizing algorithm for arbitrary interconnect tree structures under Elmore delay model. Extensive experimental results have shown that our wiresizing solution reduces interconnect delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnect delays to the timing-critical sinks by up to 12%