Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Wire Ordering for Detailed Routing
IEEE Design & Test
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model
Proceedings of the conference on Design, automation and test in Europe
Fidelity and Near-Optimality of Elmore-Based Routing Constructions
Fidelity and Near-Optimality of Elmore-Based Routing Constructions
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using well-solvable quadratic assignment problems for VLSI interconnect applications
Discrete Applied Mathematics
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Optimal ordering and sizing of wires in a constrained-width interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the Miller coupling factors (MCF) ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet near-optimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65nm process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10% in wire delay, translated to about 5% improvement in the clock cycle of a high-performance microprocessor implemented in that technology.