Optimal shielding/spacing metrics for low power design

  • Authors:
  • Ravishankar Arunachalam;Emrah Acar;Sani R. Nassif

  • Affiliations:
  • -;-;-

  • Venue:
  • ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
  • Year:
  • 2003

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Abstract

Noise arising from line-to-line coupling is a major problem fordeep submicron design, and present technology trends are causing an increase in this type of noise. Common current methods todecrease coupling noise include shielding and buffering, both ofwhich can increase overall power dissipation. An alternativemethod is spacing, which has the added benefit of improving themanufacturability (i.e.defect insensitivity) of the design. Thispaper explores the issue of coupling noise reduction, and proposes performance metrics that can be used by the designer todetermine which of the alternative methods is best suited for aspecific interconnect configuration.