Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Delay and Energy Efficient Data Transmission for On-Chip Buses
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in the literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but propagation delay is data dependent and data is application dependent. Different applications may have different data behaviors. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give inferior performance results. By exploiting similarity in the data transmitted on on-chip buses, we propose three delay minimization techniques, namely, data packing (DPack), data permutation (DPerm), and data replication with shielding and two-phase transmission (RESTP). We show that for a 5-mm 32-bit on-chip bus in 90nm CMOS technology, the DPack, DPerm, and RESTP techniques achieve more than 25%, 32%, and 51% delay savings, respectively, in both address and data buses. For a 32-bit bus, the DPack, DPerm, and RESTP techniques require 38, 34, and 48 wires, respectively.