Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A repeater optimization methodology for deep sub-micron, high-performance processors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Minimum crosstalk channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error-correction and crosstalk avoidance in DSM busses
Proceedings of the 2003 international workshop on System-level interconnect prediction
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Resource-constrained low-power bus encoding with crosstalk delay elimination
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Error-correction and crosstalk avoidance in DSM busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Joint Equalization and Coding for On-Chip Bus Communication
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fault tolerant bus architecture for deep submicron based processors
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
A low-power bus design using joint repeater insertion and coding
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Controlling inductive cross-talk and power in off-chip buses using CODECs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An energy-efficient temporal encoding circuit technique for on-chip high performance buses
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low-power bus encoding using an adaptive hybrid algorithm
Proceedings of the 43rd annual Design Automation Conference
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bus architecture for crosstalk elimination in high performance processor design
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Energy reduction through crosstalk avoidance coding in networks on chip
Journal of Systems Architecture: the EUROMICRO Journal
Forbidden transition free crosstalk avoidance CODEC design
Proceedings of the 45th annual Design Automation Conference
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
Energy efficient and high speed on-chip ternary bus
Proceedings of the conference on Design, automation and test in Europe
Energy-efficient encoding techniques for off-chip data buses
ACM Transactions on Embedded Computing Systems (TECS)
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay-efficient bus encoding techniques
Microprocessors & Microsystems
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bit-stuffing algorithm for crosstalk avoidance in high speed switching
INFOCOM'10 Proceedings of the 29th conference on Information communications
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Scalable codeword generation for coupled buses
Proceedings of the Conference on Design, Automation and Test in Europe
An error-correcting unordered code and hardware support for robust asynchronous global communication
Proceedings of the Conference on Design, Automation and Test in Europe
Throughput optimization for area-constrained links with crosstalk avoidance methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient CODEC designs for crosstalk avoidance codes based on numeral systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint equalization and coding for on-chip bus communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Computers and Electrical Engineering
Fibonacci codes for crosstalk avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects
Microelectronics Journal
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The propagation delay across long on-chip buses is increasingly becoming a limiting factor in high-speed designs. Crosstalk between adjacent wires on the bus may create a significant portion of this delay. Placing a shield wire between each signal wire alleviates the crosstalk problem but doubles the area used by the bus, an unacceptable consequence when the bus is routed using scarce top-level metal resources. Instead, we propose to employ data encoding to eliminate crosstalk delay within a bus. This paper presents a rigorous analysis of the theory behind "self-shielding codes", and gives the fundamental theoretical limits on the performance of codes with and without memory. Specifically, we find that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding.