The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Forbidden transition free crosstalk avoidance CODEC design
Proceedings of the 45th annual Design Automation Conference
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
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Low-complexity CODECs for two classes of crosstalk avoidance codes (CACs), forbidden pattern codes (FPCs) and forbidden transition codes (FTCs), have been recently proposed based on Fibonacci-based binary numeral system. In this paper, we first generalize this idea and establish a generic framework for the CODEC design of all classes of CACs based on binary mixed-radix numeral systems. Using this framework, we then propose novel CODEC designs for three important classes of CACs, one lambda codes (OLCs), FPCs, and forbidden overlapping codes (FOCs). Our CODEC designs have area complexity and delay that increase quadratically with the size of the bus, while achieving optimal or nearly optimal code rates. Our CODECs also have simple and regular circuitry, and can easily achieve very high throughput by pipelining. Our efficient CODECs, used with such techniques as partial coding, help to make CACs a practical option in combating crosstalk delay, which is a bottleneck in deep submicrometer system-on-chip designs.