A bus delay reduction technique considering crosstalk

On-chip interconnections: impact of adjacent lines on timing

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Bus encoding to prevent crosstalk delay

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Error-correction and crosstalk avoidance in DSM busses

Proceedings of the 2003 international workshop on System-level interconnect prediction

Designing fast on-chip interconnects for deep submicrometer technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Exploiting Crosstalk to Speed up On-Chip Buses

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

Proceedings of the 2004 international symposium on Low power electronics and design

Error-correction and crosstalk avoidance in DSM busses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Formal derivation of optimal active shielding for low-power on-chip buses

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime

Proceedings of the 2006 international workshop on System-level interconnect prediction

Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Serial-link bus: a low-power on-chip bus architecture

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

A robust edge encoding technique for energy-efficient multi-cycle interconnect

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Reducing interconnect delay uncertainty via hybrid polarity repeater insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Simultaneous shield and repeater insertion

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Serial-link bus: a low-power on-chip bus architecture

IEEE Transactions on Circuits and Systems Part I: Regular Papers

SSMCB: low-power variation-tolerant source-synchronous multicycle bus

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Exploiting parity computation latency for on-chip crosstalk reduction

IEEE Transactions on Circuits and Systems II: Express Briefs

Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patterns

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

Microelectronics Journal

Resource based optimization for simultaneous shield and repeater insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient RC low-power bus encoding methods for crosstalk reduction

Integration, the VLSI Journal

Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A robust edge encoding technique for energy-efficient multi-cycle interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient CODEC designs for crosstalk avoidance codes based on numeral systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips

Microprocessors & Microsystems

On the necessity of combining coding with spacing and shielding for improving performance and power in very deep sub-micron interconnects

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation