Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resource based optimization for simultaneous shield and repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Passive shielding has been used to reduce capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between the bus lines. Active shielding is another shielding technique, in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This work formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (/spl gamma/ = C/sub c//C/sub g/). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A sub-optimal active shielding architecture with simpler hardware is also proposed. Simulation results show that using the sub-optimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit.