The deep sub-micron signal integrity challenge
ISPD '99 Proceedings of the 1999 international symposium on Physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
Proceedings of the 37th Annual Design Automation Conference
Predicting coupled noise in RC circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
IEEE Transactions on Computers
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
On automatic analysis of geometrically proximate nets in VSLI layout
Proceedings of the conference on Design, automation and test in Europe
Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Shield count minimization in congested regions
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Noise Model for Multiple Segmented Coupled RC Interconnects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Crosstalk Minimization in Logic Synthesis for PLA
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Fault tolerant clockless wave pipeline design
Proceedings of the 1st conference on Computing frontiers
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Formal derivation of optimal active shielding for low-power on-chip buses
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Timing driven track routing considering coupling capacitance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Crosstalk-aware domino logic synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Crosstalk Induced Fault Analysis and Test in DRAMs
Journal of Electronic Testing: Theory and Applications
Crosstalk minimization in logic synthesis for PLAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire sizing alternative: an uniform dual-rail routing architecture
Proceedings of the conference on Design, automation and test in Europe
A multiline model for time-efficient estimation of crosstalk
Analog Integrated Circuits and Signal Processing
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
On the distribution of runs of ones in binary strings
Computers & Mathematics with Applications
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified detection scheme for crosstalk effects in interconnection bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Worst case crosstalk noise effect analysis in DSM circuits by ABCD modeling
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The performance of high-speed electronic systems is limited by interconnect-related failure modes such as coupled noise. We propose new techniques for alleviating the problems caused by coupling between signal lines on integrated circuits. We show that models used by previous work on coupled noise-constrained layout synthesis do not allow the use of several important degrees of freedom. These degrees of freedom include the ability to utilize dynamic noise margins rather than static noise margins, the dependence of coupled noise on drive strength, and the possibility of using overlaps to reduce susceptibility to noise. We derive an expression for the coupled noise integral and a bound for the peak coupled noise voltage which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work. We use the new bounds to guide a greedy channel router, which manipulates exact adjacency information at every stage, allowing it to introduce jogs or doglegs when necessary for coupled noise reduction. Experimental results indicate that our algorithm compares favorably to previous work. The coupled noise is significantly reduced on benchmark instances