Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
On testing wave pipelined circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sensing circuit for on-line detection of delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PA-RISC 2.0 architecture
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a fault tolerant design technique for clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless wave pipeline [12] which is ideally supposed to yield the theoretical maximum performance. Request signal is the most critical component for the clockless control of the wave pipelined processing of data. In practice, the request signal is very sensitive and vulnerable to electronic crosstalk noise, referred to as glitch, and this problem has become extremely stringent in the ultra-high density integrated circuits today. Electronic crosstalk noise may devastate the operational confidence level of the clockless wave pipeline. In this context, this paper characterizes the yield and reliability properties of the two-phase clockless asynchronous pipeline with respect to glitch. Based on the yield and reliability characterization, a simple yet effective fault tolerant architecture by using redundant request signals is proposed. The reliability model evaluates the impact of the request signal glitch on the overall reliability, and can be used to maneuver the proposed fault tolerant architecture. An experimental simulation is conducted to demonstrate the efficiency and effectiveness of the proposed fault tolerant technique.