Optimal layout to avoid CMOS stuck-open faults
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Sensing circuit for on-line detection of delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Compact and Highly Testable Error Indicator for Self-Checking Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
IEEE Transactions on Computers
Online Testing Approach for Very Deep-Submicron ICs
IEEE Design & Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Self-Checking Scheme for Very Fast Clocks' Skew Correction
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Fault tolerant clockless wave pipeline design
Proceedings of the 1st conference on Computing frontiers
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
TIMBER: time borrowing and error relaying for online timing error resilience
Proceedings of the Conference on Design, Automation and Test in Europe
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
ACM Transactions on Embedded Computing Systems (TECS)
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
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This paper analyses the problem of systems' on-line testingwith respect to logic errors due to crosstalk, delay andtransient faults. In particular, we show that logic errorsdue to crosstalk noise between internal, adjacent lines maybe not on-line detectable by conventional concurrent errordetection techniques using error detecting codes. Hence,a detector is proposed that allows the on-line detection ofsuch logic errors, and that is self-checking with respect to awide set of possible internal faults representative of realisticfailures, including crosstalk, delay, and transient faults.