Sensing circuit for on-line detection of delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified approach for timing verification and delay fault testing
A unified approach for timing verification and delay fault testing
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
IEEE Transactions on Computers
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Designing Networks with Error Detection Properties through the Fault-Error Relation
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Very deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these techniques to include gross-delay faults. Moreover, this approach can be exploited to detect stuck-at and bridging faults offline.