Process-Aggravated Noise (PAN): New Validation and Test Problems
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Methods to improve digital MOS macromodel accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
IEEE Transactions on Computers
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Journal of Electronic Testing: Theory and Applications
TA-PSV—Timing Analysis for Partially Specified Vectors
Journal of Electronic Testing: Theory and Applications
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Online Testing Approach for Very Deep-Submicron ICs
IEEE Design & Test
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Identification of Crosstalk Switch Failures in Domino CMOS Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selection of Crosstalk-Induced Faults in Enhanced Delay Test
Journal of Electronic Testing: Theory and Applications
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper addresses the problem of efficiently andaccurately generating two-vector tests for crosstalk inducedeffects, such as pulses, signal speedup and slowdown, in digitalcombinational circuits. These effects are becoming moreprevalent due to short signal switching times and deep submicroncircuitry. These noise effects can propagate through a circuit andcreate a logic error in a latch or at a primary output. We firstpresent a new way for predicting the output waveform producedby an inverter due to a non-square wave pulse at its input. Ourmodeling technique captures such properties as the amplitude ofa pulse and its rise/fall times and the delay through a device. Toexpedite the computation of the response of a logic gate to aninput pulse, we have developed a novel way of modeling suchgates by an equivalent inverter. We have developed a mixed-signaltest generator that incorporates classical PODEM-likestatic values as well as dynamic signals such as transitions andpulses, and timing information such as signal arrival times,rise/fall times, and gate delay. We also present a new analog costfunction that is used to guide the search process. Comparison ofresults with SPICE simulations confirms the accuracy of thisapproach. This paper focuses primarily on crosstalk inducedpulses, but these results have been extended to deal with speedupand slowdown effects.