Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Reduction of Number of Paths to be Tested in Delay Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Journal of Electronic Testing: Theory and Applications
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference 2001
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. In this paper, we address the problem of enhanced delay test considering crosstalk-induced effects. Two types of crosstalk-induced delay fault model in related works are analyzed according to their relationship to common delay fault models. The difficulties in test generation using these fault models are shown. Based on the discussion, a single precise crosstalk-induced path delay fault model, S-PCPDF model, is proposed for circuits given delay assignment. A target S-PCPDF fault gives information on a sub-path to be sensitized to generate necessary transitions coupled to a critical path. It is then convenient to enhance conventional path delay fault ATPG algorithms to implement ATPG systems for crosstalk-induced path delay faults by adding the constraints on the sub-path. We then propose two approaches to reducing the number of target S-PCPDF faults. One is based on constraints for side-inputs of paths under test. The other is based on pre-specified states during test generation for the critical path. Experimental results on ISCAS'89 benchmark circuits showed that the proposed approaches can reduce the number of target faults significantly and efficiently. The CPU time for fault list reduction and test pattern generation is acceptable for circuits of reasonable sizes.