On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Journal of Electronic Testing: Theory and Applications
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selection of Crosstalk-Induced Faults in Enhanced Delay Test
Journal of Electronic Testing: Theory and Applications
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified detection scheme for crosstalk effects in interconnection bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
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As clock speeds of current deep submicron design technologies increase over 1 GHz and metal line spacings narrow, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designer to test the effects before taping out the designs. Unfortunately, conventional tests for stuck-at or delay faults are not guaranteed to expose potential crosstalk effects. This paper presents an efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits. The ATEG (Automatic Test Extractor for Glitch) algorithm uses the multiple backtrace technique, and uses a "forward-evaluation" technique in its backtracking phase which searches for the "right" entry to select by propagating "suggested values" to minimize the number of backtracks. In the glitch propagation phase, we employ a criterion function which gives a metric for determining the propagation of a transitional signal at a given gate. Our experiments show that ATEG efficiently generates test vectors to create glitches at candidate nodes.