The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Deterministic test generation for non-classical faults on the gate level
ATS '95 Proceedings of the 4th Asian Test Symposium
Testability forecasting for sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
A simple technique for locating gate-level faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Diagnostic Test Generation for Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
A complete testing strategy based on interacting and hierarchical FSMs
Integration, the VLSI Journal
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Incremental solving techniques for SAT-based ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computational complexity in logic testing
INES'10 Proceedings of the 14th international conference on Intelligent engineering systems
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Fault isolation in grey systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
The KARL/KARATE system - automatic test pattern generation based on RT level descriptions
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
Applications of testability analysis: from ATPG to critical delay path tracing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
Considering zero-arrival time and block-arrival time in hierarchical functional timing analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Formal Verification and Diagnosis of Combinational Circuit Designs with Propositional Logic
Fundamenta Informaticae
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
VM image update notification mechanism based on pub/sub paradigm in cloud
Proceedings of the 5th Asia-Pacific Symposium on Internetware
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 14.98 |
In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster and more efficient than the PODEM algorithm reported by Goel. We also present an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits of up to 3000 gates demonstrate that the system performs test generation very fast and effectively.