Hierarchical Modeling for VLSI Circuit Testing
Hierarchical Modeling for VLSI Circuit Testing
Testing Strategy and Technique for Macro-Based Circuits
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Functional Level Primitives in Test Generation
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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An improved hierarchical testing algorithm for combinational circuits with repetitive sub-circuits using the bus fault model has been proposed. This model exploits the regularity of a circuit by grouping together identical gate-level sub-circuits into high-level sub-circuits. Though the existing test generation techniques using this model reduces the required time substantially in many cases, it fails on encountering incompatibility between the inputs and outputs of high-level modules. The algorithm proposed helps in resolving high level incompatibility. The concept of a state transition graph has been used and it has been shown that resolving incompatibility at the high level is equivalent to finding a loop in the state transition graph. The technique is hierarchical in the sense that the original modeled high-level circuit is sub-divided into a number of components as soon as an incompatibility is encountered. The results of implementation of the algorithm for a class of combinational circuits indicate a significant reduction in the test generation time and complete fault coverage thus validating our technique.