Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
2+p-SAT: relation of typical-case complexity to the nature of the phase transition
Random Structures & Algorithms - Special issue on statistical physics methods in discrete probability, combinatorics, and theoretical computer science
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Tailoring ATPG for embedded testing
Proceedings of the IEEE International Test Conference 2001
Reusing Scan Chains for Test Pattern Decompression
ETW '01 Proceedings of the IEEE European Test Workshop (ETW'01)
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Implicit test pattern generation constrained to cellular automata embedding
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
Constrained ATPG for Broadside Transition Testing
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
Power-Aware Testing and Test Strategies for Low Power Devices
Power-Aware Testing and Test Strategies for Low Power Devices
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
COMPAS -- Advanced test compressor
EWDTS '10 Proceedings of the 2010 East-West Design & Test Symposium
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new dynamic test vector compaction for automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
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Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefit from an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS'85, '89 and ITC'99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SAT-based tools for CTPG are given.