An algorithm for diagnosing two-line bridging faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Voting model based diagnosis of bridging faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Low-power multi-core ATPG to target concurrency
Integration, the VLSI Journal
Compiling problem specifications into SAT
Artificial Intelligence - Special volume on reformulation
Solution of systems of Boolean equations via the integer domain
Information Sciences: an International Journal
Bounded delay timing analysis and power estimation using SAT
Microelectronics Journal
Integration, the VLSI Journal
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
Complete SAT solver based on set theory
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
Project verification and construction of superchip tests at the RTL level
Automation and Remote Control
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
GPU-based n-detect transition fault ATPG
Proceedings of the 50th Annual Design Automation Conference
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective. It allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks