High-Level Test Generation from VHDL Behavioral Descriptions
VIUF '00 Proceedings of the VHDL International Users Forum Fall Workshop (VIUF'00)
Task Graph Extraction for Embedded System Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High-level test generation for hardware testing and software validation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Development of tests for VLSI circuit testability at the upper design levels
Automation and Remote Control
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Methods were proposed for project verification and directed design of the superchip tests represented in VHDL at the RTL level. The problem of test design and project verification was solved on the basis of the CNF-satisfiability of some system of Boolean functions.