Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
An artificial intelligence approach to test generation
An artificial intelligence approach to test generation
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Testing Strategy and Technique for Macro-Based Circuits
IEEE Transactions on Computers
Functional Level Primitives in Test Generation
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
Test Generation Algorithms for Computer Hardware Description Languages
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
Project verification and construction of superchip tests at the RTL level
Automation and Remote Control
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A novel test generation technique for large circuits with high fault coverage requirements is described. Circuit modules and signals are represented at a high descriptive level. Test data for modules are represented by predefined stimulus/ response packages which are processed symbolically using techniques derived from artificial intelligence. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. Preliminary results from a programmed implementation of the proposed test generation technique are presented.