Predicting fault detectability in combinational circuits - a new design tool?
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Critical path tracing - an alternative to fault simulation
25 years of DAC Papers on Twenty-five years of electronic design automation
STAFAN: An alternative to fault simulation
25 years of DAC Papers on Twenty-five years of electronic design automation
High-Level Test Generation for VLSI
Computer
A method for generating weighted random test pattern
IBM Journal of Research and Development
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation
IEEE Transactions on Computers
On the distribution of fault coverage and test length in random testing of combinational circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fault Coverage and Test Length Estimation for Random Pattern Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Partitioning algorithm to enhance VLSI testability
ACM-SE 36 Proceedings of the 36th annual Southeast regional conference
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Mixed-level fault coverage estimation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
Economic Effects in Design and Test
IEEE Design & Test
On the Equivalence of Fanout-Point Faults
IEEE Transactions on Computers
Test-Pattern Generation Based on Reed-Muller Coefficients
IEEE Transactions on Computers
Modeling Fault Coverage of Random Test Patterns
Journal of Electronic Testing: Theory and Applications
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
Chip partitioning aid: A design technique for partitionability and testability in VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Structured trace diagnosis for LSSD board testing—an alternative to full fault simulated diagnosis
DAC '81 Proceedings of the 18th Design Automation Conference
Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help?
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Tackling Test Trade-offs from Design, Manufacturing to Market using Economic Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly
Journal of Electronic Testing: Theory and Applications
Design for Testability A Survey
IEEE Transactions on Computers
Parallel fault backtracing for calculation of fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Paper: Automatic test pattern generation on parallel processors
Parallel Computing
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
System test cost modelling based on event rate analysis
ITC'94 Proceedings of the 1994 international conference on Test
What is the path to fast fault simulation?
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
IEEE Transactions on Computers
An analysis of the economics of self-test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ATWIG, an automatic test pattern generator with inherent guidance
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A probabilistic analysis of coverage methods
ACM Transactions on Design Automation of Electronic Systems (TODAES)
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
| Hi-index | 0.02 |
Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault simulation costs, and minimum test pattern generation costs for LSSD logic structures. The formulae are significant in projecting growth trends for test volumes and various test generation costs with increasing gate count G. Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures. Such LSSD structures are referred to as “coupled” structures. Based on empirical observation that the number of latches in an LSSD logic structure is proportional to the gate count G, it is shown that the logic test time for coupled structures grows as G2. It is also shown that (i) parallel fault simulation costs grow as G3, (ii) deductive fault simulation costs grow as G2, and (iii) the minimum test pattern generation costs grow as G2. Based on these projections some future testing problems become apparent.