Introduction to VLSI Systems
A parallel bit map processor architecture for DA algorithms
DAC '81 Proceedings of the 18th Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
The complexity of design automation problems
DAC '80 Proceedings of the 17th Design Automation Conference
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
A high performance routing engine
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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With the increasing scale of integration we need to employ DA algorithms to assist us in managing the complexities involved. Many of our current techniques are already costly and slow and yet scale by some power law as the gate count increases. An analysis of the strategies open to us leads to the possibility that in many cases specialised DA hardware is cost effective. This paper then describes a series of trials to employ a 64 x 64 distributed array processor at DA tasks. Some unexpected results were obtained as algorithms evolved in the area of tracking, simulation, placement, test generation, fault simulation, and layout rule checking. The paper concludes with a discussion of the overheads incurred in employing unconventional hardware.