A parallel bit map processor architecture for DA algorithms
DAC '81 Proceedings of the 18th Design Automation Conference
Hardware support for automatic routing
DAC '82 Proceedings of the 19th Design Automation Conference
Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help?
DAC '82 Proceedings of the 19th Design Automation Conference
An efficient variable-cost maze router
DAC '82 Proceedings of the 19th Design Automation Conference
An iterative technique for printed wire routing
DAC '74 Proceedings of the 11th Design Automation Workshop
An iterative-improvement penalty-function-driven wire routing system
IBM Journal of Research and Development
Formal specification and verification of hardware: a comparative case study
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Hi-index | 0.00 |
A hardware architecture for implementing Lee based routing algorithms is described. The design features hardware implementations of the main data structures and parallelism among a number of specialised processing elements. An engine based on this architecture has been constructed which executes a sophisticated cost-based algorithm 40 times faster than a VAX 11/780.