Formal specification and verification of hardware: a comparative case study

Authors:
V. Stavridou;H. Barringer;D. A. Edwards
Affiliations:
Department of Computer Science, University of Manchester, UK;Department of Computer Science, University of Manchester, UK;Department of Computer Science, University of Manchester, UK
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

Formal methods are applied with increased frequency in the specification and verification of digital systems as an alternative to traditional methods of establishing correctness, such as simulation and testing. This article briefly outlines the goals and the philosophy of the HArdware VErification project at the Department of Computer Science within the University of Manchester. Our objective here is to report on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems. Our strategy consists of working with incrementally “harder” test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device.