Fault-test analysis techniques based on logic simulation

• Authors: E. G. Ulrich;T. Baker;L. R. Williams
• Venue: DAC '72 Proceedings of the 9th Design Automation Workshop
• Year: 1972

In Part I of this paper we describe FANSSIM, a logic simulator whose primary use is fault analysis, i.e., fault test verification. The main feature of FANSSIM, aside from precise timing simulation, is high-speed/low-cost performance. The performance achieved ranges from 10,000 to 80,000 signals per dollar for typical simulations. Techniques contributing to this performance are: exclusive simulation of activity; a table-driven method for individual element simulation; an event-scheduling mechanism which remains economical for large, active networks; a three-state simulation method operating at high speed for 0-1 and 1-0 signals; and implementation of the central simulator subroutine in 360-Assembly Language. Additional FANSSIM capabilities not generally available in other simulators are the capability to define and use a large variety of nonprimitive logic elements without sacrificing speed or space, an oscillation-safe technique for network initialization, dynamic and accumulated activity reporting in terms of element transitions, and the transmission of nonbinary messages through a logic network. In Part II of this paper we describe three techniques for fault-test analysis. The first is a simple, economical “sensitive-state-detection” technique which determines for every element whether faults are transferred from inputs to output. This technique quickly predicts whether a given fault-test pattern is potentially successful and should be analyzed in more detail. The second fault-test analysis technique, which is used only if sensitive-state-detection promises success is an optimized single-fault-injection-and-simulation technique similar to generally known methods. This technique, although basically slow, is economically acceptable if it is used in conjunction with sensitive-state-detection and a fast simulator such as FANSSIM. The third technique is a highly economical fault propagation method based on the simultaneous simulation of the unfaulted and many single-fault machines. Economy is achieved by splitting off faulty machine simulations only if faulty machine activity diverges from good machine activity, and by recombining simulations when activity converges. For small networks this technique achieves its full potential and completes all faulty-machine simulations during a single pass.