A massively parallel algorithm for fault simulation on the connection machine
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Behavioral-Level Fault Simulation
IEEE Design & Test
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
An engine for the multi-level simulation of digital systems (simulation engine)
An engine for the multi-level simulation of digital systems (simulation engine)
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Fault simulation is an essential part of the design cycle and for large circuits it can be very time consuming. This paper examines the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally the modifications necessary to make MANSE capable of fault simulation are considered.