PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Structured trace diagnosis for LSSD board testing—an alternative to full fault simulated diagnosis
DAC '81 Proceedings of the 18th Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
STAFAN: An alternative to fault simulation
25 years of DAC Papers on Twenty-five years of electronic design automation
Extension of the critical path tracing algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A new two task algorithm for clock mode fault simulation in sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A graph compaction approach to fault simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Towards the logic defect diagnosis for partial-scan designs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Delay-Fault Diagnosis by Critical-Path Tracing
IEEE Design & Test
Fast fault simulation for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
A trace-based method for delay fault diagnosis in synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Adaptive Techniques for Improving Delay Fault Diagnosis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
PROOFS: a super fast fault simulator for sequential circuits
EURO-DAC '90 Proceedings of the conference on European design automation
A proposed hardware fault simulation engine
EURO-DAC '91 Proceedings of the conference on European design automation
Multiple-fault diagnosis based on single-fault activation and single-output observation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Spatial and temporal design debug using partial MaxSAT
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O
ITC'94 Proceedings of the 1994 international conference on Test
A parallel algorithm for fault simulation on the connection machine
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testability analysis: what role should it play in IC design?
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Evaluation of a fan out stem based fault simulation in sequential circuits
Mathematical and Computer Modelling: An International Journal
Tuning dynamic data flow analysis to support design understanding
Proceedings of the Conference on Design, Automation and Test in Europe
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We present an alternative to fault simulation, referred to as critical path tracing, that determines the faults detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. Critical path tracing is an approximate method, but the approximations introduced occur seldom and do not affect its usefulness. This method is more efficient than conventional fault simulation.