Fault simulation on massively parallel SIMD machines: algorithms, implementations and results
Journal of Electronic Testing: Theory and Applications
EURO-DAC '92 Proceedings of the conference on European design automation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Data parallel-fault simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A parallel algorithm for fault simulation based on PROOFS
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Optimizing Graph Algorithms for Improved Cache Performance
IEEE Transactions on Parallel and Distributed Systems
Cell placement on graphics processing units
Proceedings of the 20th annual conference on Integrated circuits and systems design
Multi-Level Graph Layout on the GPU
IEEE Transactions on Visualization and Computer Graphics
Larrabee: a many-core x86 architecture for visual computing
ACM SIGGRAPH 2008 papers
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Accelerating large graph algorithms on the GPU using CUDA
HiPC'07 Proceedings of the 14th international conference on High performance computing
GPU-based n-detect transition fault ATPG
Proceedings of the 50th Annual Design Automation Conference
RAG: an efficient reliability analysis of logic circuits on graphics processing units
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On the automatic generation of GPU-oriented software applications from RTL IPs
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
| Hi-index | 0.00 |
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structures are particularly computationally expensive as a large number of patterns has to be evaluated. In this work, we propose to map a fault simulation algorithm based on the parallel-pattern single-fault propagation (PPSFP) paradigm to many-core architectures and describe the involved algorithmic optimizations. Many-core architectures are characterized by a high number of simple execution units with small local memory. The proposed fault simulation algorithm exploits the parallelism of these architectures by use of parallel data structures. The algorithm is implemented for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a speed-up of up to 17x compared to an existing GPU fault-simulation algorithm and up to 16x compared to state-of-the-art algorithms on conventional processor architectures.