HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the properties of the input pattern fault model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fast fault simulation for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
Compact Dictionaries for Fault Diagnosis in Scan-BIST
IEEE Transactions on Computers
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of Integrated Design & Process Science
Parallel fault backtracing for calculation of fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing zero-aliasing space compressors: graph theory approach
MIC '07 Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control
ModelSim verification tool in testing cores-based system-on-chips
MIC '08 Proceedings of the 27th IASTED International Conference on Modelling, Identification and Control
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
Enhancing testability in architectural design for the new generation of core-based embedded systems
HASE'04 Proceedings of the Eighth IEEE international conference on High assurance systems engineering
Efficient test response compression for multiple-output circuits
ITC'94 Proceedings of the 1994 international conference on Test
CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics
Security analysis of logic obfuscation
Proceedings of the 49th Annual Design Automation Conference
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