A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Optimal Space Compaction of Test Responses
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero-aliasing space compaction using linear compactors with bounded overhead
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shrinking wide compressors [BIST]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
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In this paper a new totally error propagating compactor is proposed which can be used for arbitrary core-based designs and also for mixed signal ICs with digital interfaces. All errors at the outputs of the cores are detected at the outputs of the proposed compactor. This property is achieved with a small amount of time redundancy.