Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Space and Time Compaction Schemes for Embedded Cores
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Aliasing-Free Space and Time Compactions with Limited Overhead
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
Fault detection and diagnosis with parity trees for space compaction of test responses
Proceedings of the 43rd annual Design Automation Conference
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Space compaction is employed in built-in self-testing schemes to compress the test responses from a k-output circuit to q signature streams, where q≪k. The effectiveness of a compaction method is measured by its compaction ratio k/q and the amount of hardware required to implement the compaction circuit. However, a high compaction ratio can require a very large compactor as well as introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing linear, zero-aliasing space compactors that provide a high compaction ratio and introduce bounded hardware overhead. We develop a graph model for the space-compaction process and relate space-compactor design to the graph coloring problem. This technique can also be used to reduce the width of multiple-input signature registers that are used for response compaction. We apply our design method to the ISCAS 85 benchmark circuits and present experimental data on the compaction ratio achieved for these circuits