Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
IEEE Transactions on Computers
Programmable BIST Space Compactors
IEEE Transactions on Computers
Design of compactors for signature-analyzers in built-in self-test
Proceedings of the IEEE International Test Conference 2001
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Parity-Based Output Compaction for Core-Based SOCs
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
Synthesis of X-Tolerant Convolutional Compactors
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Modular Compactor of Test Responses
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero-aliasing space compaction using linear compactors with bounded overhead
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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While response compaction reduces the size of expected vectors that need to be stored on tester memory, the consequent information loss inevitably reflects into loss in test quality. Unknown x's further exacerbate the quality loss problem, as they mask out errors captured in other scan cells in the presence of response compactors. In this paper, we propose a technique that manipulates the x distribution in scan responses prior to their propagation into the response compactor. A block, which we refer to as x-align, inserted between the scan chains and the response compactor aligns response x's within the same slices as much as possible in order to increase the number of scan cells that can be observed through the compactor. The alignment of x's is achieved by delaying the scan-out operations in the scan chains, wherein the proper delay values are computed judiciously. We present an Integer Linear Programming (ILP) formulation and a computationally efficient greedy heuristic for the computation of the delay values for scan chains. The x-align hardware is generic yet reconfigurable. An analysis of x distribution in a captured response helps compute the proper delay values, with which x-align is reconfigured to maximize the alignment of x's. The scan cell observability enhancement delivered by x-align paves the way for the utilization of simple response compactors, such as parity trees, yet providing high levels of test quality even in the presence of a large density of response x's. X-align can also be utilized with any response compactor to manipulate the x distribution in favor of the compactor, thus improving the test quality attained.