Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Structured Logic Testing
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
A hybrid scheme for compacting test responses with unknown values
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract--A circuit may produce unknown output values during simulation of a test set, e.g., due to an unknown initial state or due to the existence of tristate elements. Unknown output values in the output response of a circuit make it impossible to determine a single unique signature for the fault-free circuit when built-in self-test is used for testing the circuit. We consider the problem of synthesizing a logic block that replaces unknown output values in the output response of a circuit with a known constant. The logic block is constructed from building blocks called comparison units. The synthesis procedure ensures that the built-in self-test scheme will be able to detect all the faults detectable by the test set applied to the circuit while allowing a single unique signature to be computed. Two variations of the synthesis procedure are considered, a two-dimensional version suitable for synchronous sequential circuits without scan and for scan circuits with multiple scan chains and a one-dimensional version suitable for scan circuits with a single scan chain.