On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Method for Consistent Fault Coverage Reporting
IEEE Design & Test
Progress in Design for Test: A Personal View
IEEE Design & Test
IC Failure Analysis: The Importance of Test and Diagnostics
IEEE Design & Test
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Combinational Test Generation for Various Classes of Acyclic Sequential Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
SCAN SYNTHESIS FOR ONE-HOT SIGNALS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Testing strategies for networks on chip
Networks on chip
Tradeoff Analysis For Producing High Quality Tests For Custom Circuits in PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Enhancing Yield at the End of the Technology Roadmap
IEEE Design & Test
Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits
ITC'94 Proceedings of the 1994 international conference on Test
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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