Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An output encoding problem and a solution technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Structured Logic Testing
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Avoiding Unknown States When Scanning Mutually Exclusive Latches
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
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Tri-state buses and pass transistor logic are used inmany complex applications to achieve high performanceand small area. Such circuits often contain logic requiringone-hot signals. In a scan-based design, one-hot values onthese signals may not be maintained during the scan-in andscan-out operations. Also, the presence of faults, theexistence of don't care conditions and the use of randompatterns for testing the circuit in a scan or BISTenvironment may lead to non-one-hot values on these onehot signals, resulting in abnormal circuit behavior andpossible circuit damage. In this paper, we present newtechniques for synthesizing scan-based designs so that one-hotvalues are maintained on the one-hot signals during allmodes of operation. One of our synthesis techniques oftengenerates designs with no area overhead - the designs aresmaller than those that do not ensure safe scan operation.In addition, we propose a scan path design that has noperformance overhead during the normal mode of operationand ensures that only valid states appear on the bistablesduring test mode, thus guaranteeing safe scan operations.