Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Selective pseudo scan: combinational ATPG with reduced scan in a full custom RISC microprocessor
DAC '93 Proceedings of the 30th international Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Cost-free scan: a low-overhead scan path design methodology
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A new complete diagnosis patterns for wiring interconnects
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Sequential redundancy identification using recursive learning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Partial Scan Testing on the Register-Transfer Level
Journal of Electronic Testing: Theory and Applications
Cost-Driven Ranking of Memory Elements for Partial Intrusion
IEEE Design & Test
Test sequence compaction by reduced scan shift and retiming
ATS '95 Proceedings of the 4th Asian Test Symposium
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Deriving Signal Constraints to Accelerate Sequential Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
SCAN SYNTHESIS FOR ONE-HOT SIGNALS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
ITC'94 Proceedings of the 1994 international conference on Test
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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