The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testability-based partial scan analysis
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
A three-stage partial scan design method to ease ATPG
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
IEEE Transactions on Computers
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting symbolic techniques for partial scan flip flop selection
Proceedings of the conference on Design, automation and test in Europe
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Partial Scan Design Based on State Transition Modeling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATS '99 Proceedings of the 8th Asian Test Symposium
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Partial Scan beyond Cycle Cutting
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Partial Scan Selection Based on Dynamic Reachability and Observability Information
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Combination of Structural and State Analysis for Partial Scan
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A comprehensive approach to the partial scan problem using implicit state enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Evolutionary design of reconfiguration strategies to reduce the test application time
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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Abstract--Partial scan design is divided into two stages: 1) critical cycle breaking and 2) partial scan flip-flop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops have been selected. The valid-state-based testability measure may become ineffective to select scan flip-flops when cycles remaining in the circuit are not so influential to testability. The method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure conflict. Sufficient experimental results are presented.