Evolutionary algorithms for VLSI CAD
Evolutionary algorithms for VLSI CAD
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Static Test Compaction for Multiple Full-Scan Circuits
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Physical Demonstration of Polymorphic Self-Checking Circuits
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently, a method has been presented that allows a significant test application time reduction if some of gates of a digital circuit are reconfigured before test is applied. Selection of the gates for reconfiguration was performed using a very time consuming deterministic recursive search algorithm. In this paper, a new method is proposed for selection of the gates in order to reduce the test application time. The method utilizes an evolutionary algorithm which is able to discover very competitive reconfiguration strategies while the time of optimization is considerably reduced with respect to the original algorithm. Moreover, the user can easily balance the trade off between the number of test vectors and amount of logic that has to be reconfigured. Experimental results are reported for the ISCAS85 benchmark suite.