Gate-level optimization of polymorphic circuits using Cartesian genetic programming
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
On the completeness of the polymorphic gate set
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary design of reconfiguration strategies to reduce the test application time
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
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Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation.