ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Proceedings of the European Conference on Genetic Programming
Providing information from the environment for growing electronic circuits through polymorphic gates
GECCO '05 Proceedings of the 7th annual workshop on Genetic and evolutionary computation
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Reducing the number of transistors in digital circuits using gate-level evolutionary design
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Novel Logic Circuits Controlled by Vdd
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Physical Demonstration of Polymorphic Self-Checking Circuits
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Evolution of polymorphic self-checking circuits
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Designing polymorphic circuits with evolutionary algorithm based on weighted sum method
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
A SAT-based fitness function for evolutionary optimization of polymorphic circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Towards new applications of multi-function logic: image multi-filtering
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Polymorphic gates are special kinds of logic gates that can exhibit different functions under the control of environmental parameters, such as light, temperature, and VDD. These polymorphic gates can be used to build polymorphic circuits that perform different functions under different environments. Because polymorphic gates are different from traditional logic gates, the existent completeness theory for the traditional logic gate set is not suitable for the polymorphic gate set. So far, only the definition of the complete polymorphic gate set is given. There is no approach to judging whether a given polymorphic gate set is complete. The contributions of this article include three aspects. First, the impact of logic-1 and logic-0 on the completeness of the polymorphic gate set is discussed. Second, the theory and two related algorithms for judging the completeness of polymorphic gate sets with two modes are given. Finally, the theory and related algorithms for complete polymorphic gate sets with more than two modes are proposed.