Fault-tolerant computer system design
Fault-tolerant computer system design
Digital Design: Principles and Practices
Digital Design: Principles and Practices
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Partially Duplicated Code-Disjoint Carry-Skip Adder
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Reversibility for efficient computing
Reversibility for efficient computing
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
IEEE Transactions on Computers
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On bifunctional polymorphic gates controlled by a special signal
WSEAS Transactions on Circuits and Systems
Gate-level optimization of polymorphic circuits using Cartesian genetic programming
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
On the completeness of the polymorphic gate set
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents elementary circuit components which exhibit self-checking properties; however, which do not utilize any additional signals to indicate the fault. The fault is indicated by generating specific values at some of standard outputs of a given circuit. In particular, various evolved adders containing conventional as well as polymorphic gates are proposed with less than duplication overhead which are able to detect a reasonable number of stuck-at-faults by oscillations at the carry-out output when the control signal of polymorphic gates oscillates.