The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
A Scalable Approach to Evolvable Hardware
Genetic Programming and Evolvable Machines
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Proceedings of the European Conference on Genetic Programming
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
A multi-chromosome approach to standard and embedded cartesian genetic programming
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Physical Demonstration of Polymorphic Self-Checking Circuits
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Evolution of polymorphic self-checking circuits
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
The Automatic Acquisition, Evolution and Reuse of Modules in Cartesian Genetic Programming
IEEE Transactions on Evolutionary Computation
Generalized Disjunction Decomposition for Evolvable Hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers
Proceedings of the 12th annual conference companion on Genetic and evolutionary computation
GECCO 2011 tutorial: cartesian genetic programming
Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
GECCO 2012 tutorial: cartesian genetic programming
Proceedings of the 14th annual conference companion on Genetic and evolutionary computation
GECCO 2013 tutorial: cartesian genetic programming
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
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Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods (such as BDD, Espresso or ABC System) and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits - Multiplier/Sorter and Parity/Majority circuits of variable input size.