Towards the Automatic Design of More Efficient Digital Circuits

  • Authors:

  • Vesselin K. Vassilev;Dominic Job;Julian F. Miller

  • Affiliations:

  • -;-;-

  • Venue:
  • EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
  • Year:
  • 2000

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Abstract

This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping to represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values.Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits can be explored.The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of 23 two-input logic gates that in terms of number of two-input gates used is 23: 3 percentages more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are 14 ANDs, 9 XORs, and 2 inversions (NOT). The evolved four-bit multiplier consists of 57 two-input logic gates that are 10: 9 percentages more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs.