Low power realization of finite state machines—a decomposition approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Adaptive Equalization of Digital Communication Channels Using Evolvable Hardware
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Hardware Evolution at Function Level
PPSN IV Proceedings of the 4th International Conference on Parallel Problem Solving from Nature
Proceedings of the European Conference on Genetic Programming
A Divide-and-Conquer Approach to Evolvable Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
HereBoy: A Fast Evolutionary Algorithm
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Evolution of Analog Circuits on Field Programmable Transistor Arrays
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Towards Evolvable IP Cores for FPGAs
EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits
Genetic Programming and Evolvable Machines
Bias and scalability in evolutionary development
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
On Evolution of Relatively Large Combinational Logic Circuits
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Evolved Digital Circuits and Genome Complexity
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Evolution of Asynchronous Sequential Circuits
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Development Brings Scalability to Hardware Evolution
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Evolving Redundant Structures for Reliable Circuits - Lessons Learned
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Adaptive and Evolvable Hardware - A Multifaceted Analysis
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Solving the even-n-parity problems using Best SubTree Genetic Programming
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Adaptive Salt-&-Pepper Noise Removal: A Function Level Evolution based Approach
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Fitness landscape analysis and image filter evolution using functional-level CGP
EuroGP'07 Proceedings of the 10th European conference on Genetic programming
WCCI'08 Proceedings of the 2008 IEEE world conference on Computational intelligence: research frontiers
Implementing multi-VRC cores to evolve combinational logic circuits in parallel
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
An intrinsic evolvable hardware based on multiplexer module array
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Research on fault-tolerance of analog circuits based on evolvable hardware
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Partitioned incremental evolution of hardware using genetic programming
EuroGP'08 Proceedings of the 11th European conference on Genetic programming
Hardware accelerators for Cartesian genetic programming
EuroGP'08 Proceedings of the 11th European conference on Genetic programming
Digital filter design using evolvable hardware chip for image enhancement
ICIC'06 Proceedings of the 2006 international conference on Intelligent Computing - Volume Part I
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Real-world applications of analog and digital evolvable hardware
IEEE Transactions on Evolutionary Computation
A family of compact genetic algorithms for intrinsic evolvable hardware
IEEE Transactions on Evolutionary Computation
Generalized Disjunction Decomposition for Evolvable Hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing combinational circuits with an evolutionary algorithm based on the repair technique
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Hi-index | 0.00 |
Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD---ES, which combines the 3SD method with the (μ, 驴) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD---ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.