Reducing the number of transistors in digital circuits using gate-level evolutionary design
Proceedings of the 9th annual conference on Genetic and evolutionary computation
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Fast evolution of large digital circuits
WSEAS Transactions on Computers
Intrinsic evolution of digital circuits using evolutionary algorithms
Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation
A three-step decomposition method for the evolutionary design of sequential logic circuits
Genetic Programming and Evolvable Machines
Gate-level optimization of polymorphic circuits using Cartesian genetic programming
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Adaptive combinational logic circuits based on intrinsic evolvable hardware
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
An intrinsic evolvable hardware based on multiplexer module array
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Evolutionary design of generic combinational multipliers using development
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Designing combinational circuits with an evolutionary algorithm based on the repair technique
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Genetic Programming and Evolvable Machines
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
Evolvable hardware design based on a novel simulated annealing in an embedded system
Concurrency and Computation: Practice & Experience
On the Evolution of Hardware Circuits via Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1+lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided